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1. general description the 74aup1t58 provides low-power, low-voltage con?gurable logic gate functions. the output state is determined by eight patterns of 3-bit input. the user can choose the logic functions and, or, nand, nor, xor, inverter and buffer. all inputs can be connected to v cc or gnd. this device ensures a very low static and dynamic power consumption across the entire v cc range from 2.3 v to 3.6 v. the 74aup1t58 is designed for logic-level translation applications with input switching levels that accept 1.8 v low-voltage cmos signals, while operating from either a single 2.5 v or 3.3 v supply voltage. the wide supply voltage range ensures normal operation as battery voltage drops from 3.6 v to 2.3 v. this device is fully speci?ed for partial power-down applications using i off . the i off circuitry disables the output, preventing the damaging back?ow current through the device when it is powered down. schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire v cc range. 2. features n wide supply voltage range from 2.3 v to 3.6 v n high noise immunity n esd protection: u hbm jesd22-a114f class 3a exceeds 5000 v u mm jesd22-a115-a exceeds 200 v u cdm jesd22-c101c exceeds 1000 v n low static power consumption; i cc = 1.5 m a (maximum) n latch-up performance exceeds 100 ma per jesd 78b class ii n inputs accept voltages up to 3.6 v n low noise overshoot and undershoot < 10 % of v cc n i off circuitry provides partial power-down mode operation n multiple package options n speci?ed from - 40 cto+85 c and - 40 c to +125 c 74aup1t58 low-power con?gurable gate with voltage-level translator rev. 02 29 september 2009 product data sheet
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 2 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram table 1. ordering information type number package temperature range name description version 74aup1t58gw - 40 c to +125 c sc-88 plastic surface-mounted package; 6 leads sot363 74aup1t58gm - 40 c to +125 c xson6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1.45 0.5 mm sot886 74aup1t58gf - 40 c to +125 c xson6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1 0.5 mm sot891 table 2. marking type number marking code [1] 74aup1t58gw a8 74aup1t58gm a8 74aup1t58gf a8 fig 1. logic symbol y c b a 6 1 3 4 001aab687
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 3 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 6. pinning information 6.1 pinning 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level. fig 2. pin con?guration sot363 (sc-88) fig 3. pin con?guration sot886 (xson6) fig 4. pin con?guration sot891 (xson6) 74aup1t58 bc gnd ay 001aah836 1 2 3 6 v cc 5 4 74aup1t58 gnd 001aah837 b a v cc c y transparent top view 2 3 1 5 4 6 74aup1t58 gnd 001aah838 b a v cc c y transparent top view 2 3 1 5 4 6 table 3. pin description symbol pin description b 1 data input gnd 2 ground (0 v) a 3 data input y 4 data output v cc 5 supply voltage c 6 data input table 4. function table [1] input output c b a y llll llhh lhll l hhh hllh hl hh hhl l hhhl
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 4 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 7.1 logic con?gurations table 5. function selection table logic function figure 2-input nand see figure 5 2-input nand with both inputs inverted see figure 8 2-input and with inverted input see figure 6 and 7 2-input nor with inverted input see figure 6 and 7 2-input or see figure 8 2-input or with both inputs inverted see figure 5 2-input xor see figure 9 buffer see figure 10 inverter see figure 11 fig 5. 2-input nand gate or 2-input or gate with both inputs inverted fig 6. 2-input and gate with input b inverted or 2-input nor gate with inverted c input 001aab688 b b6 y c 1 5 2 4 3y y c b c v cc 001aab689 b b6 y c 1 5 2 4 3y y c b c v cc fig 7. 2-input and gate with input c inverted or 2-input nor gate with inverted a input fig 8. 2-input or gate or 2-input nand gate with both inputs inverted 001aab690 a a 6 y c 1 5 2 4 3y y c a c v cc 001aab691 a 6c 1 5 2 4 3y v cc a y c y a c fig 9. 2-input xor gate fig 10. buffer 001aab692 b6c 1 5 2 4 3y v cc y b c 001aab693 a a 6 y 1 5 2 4 3y v cc
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 5 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 8. limiting values [1] the minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for sc-88 package: above 87.5 c the value of p tot derates linearly with 4.0 mw/k. for xson6 packages: above 118 c the value of p tot derates linearly with 7.8 mw/k. 9. recommended operating conditions fig 11. inverter 001aab694 b b6 y 1 5 2 4 3y v cc table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v i ik input clamping current v i <0v - 50 - ma v i input voltage [1] - 0.5 +4.6 v i ok output clamping current v o <0v - 50 - ma v o output voltage active mode and power-down mode [1] - 0.5 +4.6 v i o output current v o =0 vtov cc - 20 ma i cc supply current - 50 ma i gnd ground current - 50 - ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 c to +125 c [2] - 250 mw table 7. recommended operating conditions symbol parameter conditions min max unit v cc supply voltage 2.3 3.6 v v i input voltage 0 3.6 v v o output voltage active mode 0 v cc v power-down mode; v cc = 0 v 0 3.6 v t amb ambient temperature - 40 +125 c
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 6 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 10. static characteristics table 8. static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = 25 c v t+ positive-going threshold voltage v cc = 2.3 v to 2.7 v 0.60 - 1.10 v v cc = 3.0 v to 3.6 v 0.75 - 1.16 v v t - negative-going threshold voltage v cc = 2.3 v to 2.7 v 0.35 - 0.60 v v cc = 3.0 v to 3.6 v 0.50 - 0.85 v v h hysteresis voltage (v h = v t+ - v t - ) v cc = 2.3 v to 2.7 v 0.23 - 0.60 v v cc = 3.0 v to 3.6 v 0.25 - 0.56 v v oh high-level output voltage v i = v t+ or v t - i o = - 20 m a; v cc = 2.3 v to 3.6 v v cc - 0.1 - - v i o = - 2.3 ma; v cc = 2.3 v 2.05 - - v i o = - 3.1 ma; v cc = 2.3 v 1.9 - - v i o = - 2.7 ma; v cc = 3.0 v 2.72 - - v i o = - 4.0 ma; v cc = 3.0 v 2.6 - - v v ol low-level output voltage v i = v t+ or v t - i o = 20 m a; v cc = 2.3 v to 3.6 v - - 0.10 v i o = 2.3 ma; v cc = 2.3 v - - 0.31 v i o = 3.1 ma; v cc = 2.3 v - - 0.44 v i o = 2.7 ma; v cc = 3.0 v - - 0.31 v i o = 4.0 ma; v cc = 3.0 v - - 0.44 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.1 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.1 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.2 m a i cc supply current v i = gnd or v cc ; i o = 0 a; v cc = 2.3 v to 3.6 v - - 1.2 m a c i input capacitance v cc = 0 v to 3.6 v; v i = gnd or v cc - 0.8 - pf c o output capacitance v o = gnd; v cc = 0 v - 1.7 - pf t amb = - 40 c to +85 c v t+ positive-going threshold voltage v cc = 2.3 v to 2.7 v 0.60 - 1.10 v v cc = 3.0 v to 3.6 v 0.75 - 1.19 v v t - negative-going threshold voltage v cc = 2.3 v to 2.7 v 0.35 - 0.60 v v cc = 3.0 v to 3.6 v 0.50 - 0.85 v v h hysteresis voltage (v h = v t+ - v t - ) v cc = 2.3 v to 2.7 v 0.10 - 0.60 v v cc = 3.0 v to 3.6 v 0.15 - 0.56 v
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 7 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator v oh high-level output voltage v i = v t+ or v t - i o = - 20 m a; v cc = 2.3 v to 3.6 v v cc - 0.1 - - v i o = - 2.3 ma; v cc = 2.3 v 1.97 - - v i o = - 3.1 ma; v cc = 2.3 v 1.85 - - v i o = - 2.7 ma; v cc = 3.0 v 2.67 - - v i o = - 4.0 ma; v cc = 3.0 v 2.55 - - v v ol low-level output voltage v i = v t+ or v t - i o = 20 m a; v cc = 2.3 v to 3.6 v - - 0.1 v i o = 2.3 ma; v cc = 2.3 v - - 0.33 v i o = 3.1 ma; v cc = 2.3 v - - 0.45 v i o = 2.7 ma; v cc = 3.0 v - - 0.33 v i o = 4.0 ma; v cc = 3.0 v - - 0.45 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.5 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.5 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.5 m a i cc supply current v i = gnd or v cc ; i o = 0 a; v cc = 2.3 v to 3.6 v - - 1.5 m a d i cc additional supply current v cc = 2.3 v to 2.7 v; i o = 0 a [1] --4 m a v cc = 3.0 v to 3.6 v; i o = 0 a [2] --12 m a t amb = - 40 c to +125 c v t+ positive-going threshold voltage v cc = 2.3 v to 2.7 v 0.60 - 1.10 v v cc = 3.0 v to 3.6 v 0.75 - 1.19 v v t - negative-going threshold voltage v cc = 2.3 v to 2.7 v 0.33 - 0.64 v v cc = 3.0 v to 3.6 v 0.46 - 0.85 v v h hysteresis voltage (v h = v t+ - v t - ) v cc = 2.3 v to 2.7 v 0.10 - 0.60 v v cc = 3.0 v to 3.6 v 0.15 - 0.56 v v oh high-level output voltage v i = v t+ or v t - i o = - 20 m a; v cc = 2.3 v to 3.6 v v cc - 0.11 - - v i o = - 2.3 ma; v cc = 2.3 v 1.77 - - v i o = - 3.1 ma; v cc = 2.3 v 1.67 - - v i o = - 2.7 ma; v cc = 3.0 v 2.40 - - v i o = - 4.0 ma; v cc = 3.0 v 2.30 - - v v ol low-level output voltage v i = v t+ or v t - i o = 20 m a; v cc = 2.3 v to 3.6 v - - 0.11 v i o = 2.3 ma; v cc = 2.3 v - - 0.36 v i o = 3.1 ma; v cc = 2.3 v - - 0.50 v i o = 2.7 ma; v cc = 3.0 v - - 0.36 v i o = 4.0 ma; v cc = 3.0 v - - 0.50 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.75 m a table 8. static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 8 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator [1] one input at 0.3 v or 1.1 v, other input at v cc or gnd. [2] one input at 0.45 v or 1.2 v, other input at v cc or gnd. 11. dynamic characteristics i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.75 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.75 m a i cc supply current v i = gnd or v cc ; i o = 0 a; v cc = 2.3 v to 3.6 v - - 3.5 m a d i cc additional supply current v cc = 2.3 v to 2.7 v; i o = 0 a [1] --7 m a v cc = 3.0 v to 3.6 v; i o = 0 a [2] --22 m a table 8. static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 9. dynamic characteristics voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 13 . symbol parameter conditions 25 c - 40 c to +125 c unit min typ [1] max min max (85 c) max (125 c) v cc = 2.3 v to 2.7 v; v i = 1.65 v to 1.95 v t pd propagation delay a, b, c to y; see figure 12 [2] c l = 5 pf 2.1 3.6 5.6 0.5 6.8 7.5 ns c l = 10 pf 2.6 4.1 6.2 1.0 7.9 8.7 ns c l = 15 pf 3.0 4.6 6.8 1.0 8.7 9.6 ns c l = 30 pf 4.0 5.8 8.1 1.5 10.8 11.9 ns v cc = 2.3 v to 2.7 v; v i = 2.3 v to 2.7 v t pd propagation delay a, b, c to y; see figure 12 [2] c l = 5 pf 1.7 3.4 5.5 0.5 6.0 6.6 ns c l = 10 pf 2.2 4.0 6.2 1.0 7.1 7.9 ns c l = 15 pf 2.6 4.5 6.8 1.0 7.9 8.7 ns c l = 30 pf 3.5 5.6 8.1 1.5 10.0 11.0 ns v cc = 2.3 v to 2.7 v; v i = 3.0 v to 3.6 v t pd propagation delay a, b, c to y; see figure 12 [2] c l = 5 pf 1.4 3.2 5.1 0.5 5.5 6.1 ns c l = 10 pf 1.9 3.7 5.8 1.0 6.5 7.2 ns c l = 15 pf 2.2 4.2 6.3 1.0 7.4 8.2 ns c l = 30 pf 3.2 5.4 7.7 1.5 9.5 10.5 ns v cc = 3.0 v to 3.6 v; v i = 1.65 v to 1.95 v t pd propagation delay a, b, c to y; see figure 12 [2] c l = 5 pf 2.0 2.9 4.0 0.5 8.0 8.8 ns c l = 10 pf 2.4 3.5 4.7 1.0 8.5 9.4 ns c l = 15 pf 2.8 3.9 5.3 1.0 9.1 10.1 ns c l = 30 pf 3.6 5.1 6.7 1.5 9.8 10.8 ns
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 9 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator [1] all typical values are measured at nominal v cc . [2] t pd is the same as t plh and t phl . [3] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; s (c l v cc 2 f o ) = sum of the outputs. v cc = 3.0 v to 3.6 v; v i = 2.3 v to 2.7 v t pd propagation delay a, b, c to y; see figure 12 [2] c l = 5 pf 1.6 2.8 4.4 0.5 5.3 5.9 ns c l = 10 pf 2.1 3.4 5.1 1.0 6.1 6.8 ns c l = 15 pf 2.4 3.9 5.6 1.0 6.8 7.5 ns c l = 30 pf 3.4 5.0 7.0 1.5 8.5 9.4 ns v cc = 3.0 v to 3.6 v; v i = 3.0 v to 3.6 v t pd propagation delay a, b, c to y; see figure 12 [2] c l = 5 pf 1.3 2.8 4.4 0.5 4.7 5.2 ns c l = 10 pf 1.7 3.3 5.1 1.0 5.7 6.3 ns c l = 15 pf 2.1 3.8 5.7 1.0 6.2 6.9 ns c l = 30 pf 3.1 4.9 7.0 1.5 7.8 8.6 ns t amb = 25 c c pd power dissipation capacitance f i = 1 mhz; v i = gnd to v cc [3] v cc = 2.3 v to 2.7 v - 3.6 - - - - pf v cc = 3.0 v to 3.6 v - 4.3 - - - - pf table 9. dynamic characteristics continued voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 13 . symbol parameter conditions 25 c - 40 c to +125 c unit min typ [1] max min max (85 c) max (125 c)
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 10 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 12. waveforms measurement points are given in t ab le 10 . v ol and v oh are typical output voltage levels that occur with the output load. fig 12. input a, b and c to output y propagation delay times y output a, b, c input y output gnd v i v oh v oh v ol v ol v m v m v m v m v m v m t plh t plh t phl t phl 001aab593 table 10. measurement points supply voltage output input v cc v m v m v i t r = t f 2.3 v to 3.6 v 0.5 v cc 0.5 v i 1.65 v to 3.6 v 3.0 ns
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 11 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator [1] for measuring enable and disable times r l =5k w , for measuring propagation delays, setup and hold times and pulse width r l =1m w . test data is given in t ab le 11 . de?nitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 13. load circuitry for switching times 001aac521 dut r t v i v o v ext v cc r l 5 k w c l g table 11. test data supply voltage load v ext v cc c l r l [1] t plh , t phl t pzh , t phz t pzl , t plz 2.3 v to 3.6 v 5 pf, 10 pf, 15 pf and 30 pf 5 k w or 1 m w open gnd 2 v cc
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 12 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 13. package outline fig 14. package outline sot363 (sc-88) references outline version european projection issue date iec jedec jeita sot363 sc-88 wb m b p d e 1 e pin 1 index a a 1 l p q detail x h e e v m a a b y 0 1 2 mm scale c x 13 2 4 5 6 plastic surface-mounted package; 6 leads sot363 unit a 1 max b p cd e e 1 h e l p qy w v mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.1 0.2 dimensions (mm are the original dimensions) 0.45 0.15 0.25 0.15 a 1.1 0.8 04-11-08 06-03-16
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 13 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator fig 15. package outline sot886 (xson6) terminal 1 index area references outline version european projection issue date iec jedec jeita sot886 mo-252 sot886 04-07-15 04-07-22 dimensions (mm are the original dimensions) xson6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 0 1 2 mm scale notes 1. including plating thickness. 2. can be visible in some manufacturing processes. unit mm 0.25 0.17 1.5 1.4 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.5 0.6 a (1) max 0.5 0.04 1 6 2 5 3 4 6 (2) 4 (2) a
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 14 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator fig 16. package outline sot891 (xson6) terminal 1 index area references outline version european projection issue date iec jedec jeita sot891 sot891 05-04-06 07-05-15 xson6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 0 1 2 mm scale dimensions (mm are the original dimensions) unit mm 0.20 0.12 1.05 0.95 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.35 0.55 a max 0.5 0.04 1 6 2 5 3 4 a 6 (1) 4 (1) note 1. can be visible in some manufacturing processes.
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 15 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 14. abbreviations 15. revision history table 12. abbreviations acronym description cdm charged device model cmos complementary metal oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model table 13. revision history document id release date data sheet status change notice supersedes 74aup1t58_2 20090929 product data sheet - 74aup1t58_1 ? t ab le 2 : marking code changed from p8 into a8. ? t ab le 6 : derating factor xson6 packages has been changed. 74aup1t58_1 20080306 product data sheet - -
74aup1t58_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 29 september 2009 16 of 17 nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors 74aup1t58 low-power con?gurable gate with voltage-level translator ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 29 september 2009 document identifier: 74aup1t58_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 3 7.1 logic con?gurations . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 recommended operating conditions. . . . . . . . 5 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 17 contact information. . . . . . . . . . . . . . . . . . . . . 16 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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